Chip Check Feature — Intel® SDE documentation

# Chip Check Feature

One of the main emulation services that Intel® SDE provides is the chip-check feature. This service checks that every dynamically executed instruction is legal for the input chip. When detecting an illegal instruction, the process will exit with an error message of the form:

    % sde -skl -- myapp
    TID 0 SDE-ERROR: Executed instruction not valid for specified chip (SKYLAKE): 0x40118c rdpid rax
    Image: myapp+0x118c
    Function: test1
    Instruction bytes are: f3 48 0f c7 f8

Optionally, Intel® SDE can also emit a call-stack of the execution path that leads to the invalid instruction, or to only report the illegal instructions to an output file (and continue).

Intel® SDE allows the user to define the chip from a long list of old and new CPUs. In certain cases this check is too strict, for example when the defined chip is older than the host CPU, and the system libraries execute instructions which are not legal for the input chip.

Another usage model is to define which instructions are legal for this run based on an input CPUID definition. This means that the user defines its own CPUID behavior and chip-check will allow execution of only the instructions which are available (and legal) as defined for this CPU. More information is available in the CPUID Emulation section.

The chip-check module can also dump the list of available chips, or to dump all the XED IFORMs legal for the input chip.

Note

When specifying the chip knob in Intel® SDE command line, you actually define the CPUID behavior and the corresponding chip for the chip-check feature.

## Checking for AVX10/256 Vector Register Length

Intel® AVX10 is a converged vector ISA for all future processors. This means that Intel® AVX10 instructions will be supported on both the Performance-cores and the Efficient-cores. The converged ISA will be limited to 256 bits vector register length.

Intel® SDE provides a few options for checking that your software is ready for Intel® AVX10 256 bits vector length mode:

- Use a special knob -chip-check-vl256, this knob checks that all executed instructions are legal for 256 bits vector length mode regardless of the emulated CPU. However, your CPU definition might provide the Intel® AVX-512 feature bits and dynamic code dispatch is free to choose code path with Intel® AVX-512 instructions. Therefore, either choose CPU without Intel® AVX-512 features or limit the checks to the executable by choosing -chip-check-exe-only knob.

- Use a custom CPUID definition file that has no Intel® AVX-512 feature bits but has the required settings for Intel® AVX10 limited to 256 bits vector length. Use chip checks against the CPUID mode as defined by using the knob -chip-check-cpuid.

- Use the -gnr256 chip knob. This knob represents an artificial CPU definition that matches future processors based on Granite Rapids microarchitecture but without Intel® AVX-512 feature bits and limited to 256 bits vector length. This knob was added to make it easy to verify that your software is ready for future processors with Intel® AVX10 ISA limited to 256 bits vector length.

Chip-check controls

`-chip_check`

  Restrict to a specific XED chip [no default value]

`-chip_check_call_stack`

  Emit the call stack on error [default 0]

`-chip_check_call_stack_depth`

  Specify chip-check call-stack max depth [default 10]

`-chip_check_cpuid`

  Check against features in the active CPUID definition [default 0]

`-chip_check_die`

  Die on errors. 0=warn, 1=die [default 1]

`-chip_check_disable`

  Disable the chip checking mechanism [default 0]

`-chip_check_emit_file`

  Emit messages to a file. 0=no file, 1=file [default 0]

`-chip_check_exe_only`

  Check only the main executable [default 0]

`-chip_check_file`

  Output file chip-check errors [default sde-chip-check.txt]

`-chip_check_image`

  Repeatable knob to specify which images to check [no default value]

`-chip_check_list`

  List valid chip names and exit [default 0]

`-chip_check_list_iforms`

  List valid XED IFORMs for a specific chip and exit [default 0]

`-chip_check_stderr`

  Try to emit messages to stderr. 0=no stderr, 1=stderr [default 1]

`-chip_check_vl256`

  Check that instructions are supported in AVX10/256 vector length mode [default 0]

`-chip_check_vsyscall`

  Enable the chip checking checking in the VSYSCALL area (Linux only) [default 0]

`-chip_check_win_sys_ignore`

  Disable the chip checking in Windows NTDLL library (Windows only) [default 1]

`-chip_check_zcnt`

  The TSCNT/LZCNT has backward compatibility, check it explicitly anyway [default 0]